A 4-μm Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65-nm CMOS

Abstract

This brief reports a small size single-photon avalanche diode (SPAD) in baseline 65-nm CMOS suitable for low-cost time-of-flight application with high spatial resolution. By exploiting the less-doped n-well region to surround the vertical p-well/deep-n-well multiplication region, the electric field at the SPAD periphery can be reduced without process modifications while avoiding premature lateral breakdown. Validated using TCAD simulations, the fabricated 4- $\mu \text{m}$ diameter SPAD device exhibits a compact device size with a low dark count (73 cps/ $\mu \text{m}^{{{2}}}$ at 20 °C) and a high fill factor (17.7%) using 65-nm baseline CMOS, while demonstrating competitive performance when compared with the state of the art.