Abstract
A 4 GHz ΔΣ fractional-N frequency synthesizer for wireless communications applications is implemented in a 0.35 μm BiCMOS process. The synthesizer achieves a close-in phase noise of −66 dBc/Hz. The key building blocks are an ECL multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation, a digital third-order MASH ΔΣ-modulator that controls the modulus of the prescaler, a very linear phase detector that enables the synthesizer to achieve a low close-in phase noise, and a chargepump providing a constant output current over a large output voltage range. The power dissipation of the synthesizer chip is 27.7 mW from a 2.7 V supply.
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