A 4.5-GHz 130-nm 32-kb L0 cache with a leakage-tolerant self reverse-bias bitline scheme

Abstract

This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology. The local bitline uses a leakage-tolerant self reverse-bias (SRB) scheme with nMOS source-follower pullup access transistors, while preserving robust full-swing operation. Gate-source underdrive of -220 mV on the bitline read-select transistors is established without external bias voltages or gate-oxide overstress. Device-level measurements in the 130-nm technology show 72/spl times/ bitline active leakage reduction, enabling low-V/sub TH/ usage, 40% bitline keeper downsizing, and 16 bitcells/bitline. 11% faster read delay and 2/spl times/ higher dc noise robustness are achieved compared with high-performance dual-V/sub TH/ bitline scheme. Sustained performance and robustness benefits of the SRB technique against conventional dynamic bitline with scaling to 100- and 70-nm technology is also presented.