Abstract
The growing market demand for low-power, high-performance radio frequency blocks for effective short-range communication applications, such as home automation, smart wearables, healthcare monitoring, and automotive sensors, is addressed in this work by proposing an RF down-converter (RFDC) network. This work aims to achieve high linearity, low noise figure and high gain simultaneously by optimally splitting the performance between the three stages of the RFDC. The proposed down-conversion system is designed in UMC 180 nm CMOS process technology and the post-layout simulations on RC parasitic values with Cadence SpectreRF shows an IIP3 of 4.25 dBm and an IIP2 of 93.49 dBm. The RFDC provides a peak conversion gain of 19.4 dB and minimum double-sideband noise figure (DSB-NF) of 16.21 dB while consuming only 7.8 mW of power from a 1.5 V supply. The proposed RFDC occupies a chip area of only 0.27mm2.
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