Abstract
A low-phase-noise Σ-Δ fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator (VCO) is designed with modified digital controlled capacitor array (DCCA) to extend tuning range and minimize phase noise. A high-resolution adaptive frequency calibration (AFC) technique is proposed to choose frequency bands automatically in short time and increase phase noise immunity. A prototype is implemented in 0.13 μm CMOS technology. Experimental results show that the designed 1.2V wideband frequency synthesizer is locked from 3.05GHz to 5.17GHz within 30μs (20ppm), including 8μs AFC time. The measured in-band phase noise is −95.5 and −101dBc/Hz for 1.955GHz and 948MHz carriers, respectively, and accordingly the out-of-band phase noise is −123, −132dBc/Hz at 1MHz offset, and the reference spur is less than −69dBc.
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