A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications

Abstract

In the proposed work, 3–7 GHz two-stage Ultra-Wide-Band (UWB) power amplifier has been designed and simulated using UMC 0.18 μm CMOS technology. The proposed Power Amplifier (PA) design exhibits the simplest topology to fulfill the requirement of low gain ripple, good linearity, and small group delay variations all simultaneously for Ultra-Wide-Band (UWB) application and covering only 0.75 mm2 area of silicon. In order to obtain low gain ripple, good group delay variations and linearity at the same time, the inductive peaking and class-AB operation are employed at both the stages. The post-layout simulation results show lowest gain ripple of 19 ± 0.3 dB, good input and output matching (<−7.5 and <−6 dB), moderate group delay (±200 ps), unconditional stability, good linearity, and low power performance simultaneously for the 3–7 GHz UWB band. The design of power amplifier with these features is found to be suitable for commercial mobile or Group 1–3 of MB-OFDM UWB transmitters.KeywordsCMOS RF integrated circuitsCascode amplifierFeedbackLowest gain rippleShunt peaking