A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology

Abstract

This paper introduces a hybrid charge pump (HCP) architecture. The HCP enables high-voltage dc outputs in a nanometer-scale CMOS technology at improved power efficiency by optimally mixing different charge pump (CP) types that trade off voltage range and power efficiency. Conventional CP outputs in a bulk CMOS process are limited to a single-diode breakdown voltage (~12 V in a 65-nm technology node). To support >12 V outputs, the HCP extends the voltage tolerance of bulk CMOS substrates via two technology methods: double-diode substrate isolation and field oxide isolation. To enable these isolation methods, two specialized CP cells are devised: an all-nMOS voltage doubler and an improved-drive Dickson-type pump. Two HCP design examples with opposite voltage polarities are implemented in a 65-nm CMOS technology, and their measurement results are discussed. The positive voltage HCP achieves a 36 V output and 49% peak efficiency at a 20-μA load current and occupies 0.18 mm 2 in area. This output voltage represents a 3× increase in the technology's voltage range compared to ranges attainable by conventional designs.