A 3.3 V high speed CMOS PLL with a two-stage self-feedback ring oscillator

Abstract

A 3.3 V PLL (Phase Locked loop) is designed for high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of the VCO (Voltage Controlled Oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30 MHz/spl sim/1 GHz with a good linearity. The DC-DC voltage up/down converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 /spl mu/m n-well CMOS process. The simulation results show a locking time of 2.6 /spl mu/s at 1 GHz, lock in range of 100 MHz/spl sim/1 GHz, and a power dissipation of 112 mW.