A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations

Abstract

Recent hardware accelerators based on FPGA –[2] and ASIC –[4] have demonstrated high throughput and energy-efficient processing of path planning for applications, including the manipulation of arm-robots on a high-resolution map [1] and the autonomous navigation of battery-powered micro-robots [4]. The accelerators have focused on demonstrating the modified shortest path planning algorithms, such as extended-stride A$\ast$ [1] and dual-tree rapid-exploring random tree (RRT) [4], and achieved much higher throughput and energy efficiency (two-to-three orders of magnitude higher) than traditional implementations with CPU and GPU. A two-dimensional processing element (PE) array [5] was proposed as an alternative computing paradigm for searching the shortest path based on the expansion of wavefront in the time-domain. The time-domain delay accumulation was used for finding the shortest paths by accumulating time delays while propagating through the PEs that correspond to the pixels in a two-dimensional searching space. However, it still follows the existing A$\ast$ algorithm using an extra gradient control circuit with resistor ladders to estimate the remaining distances, resulting in inaccurate results (i.e. sub-optimal paths) with extra hardware and energy overhead.