A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS Process

Abstract

This article presents a 32-GHz frequency modulated continuous wave (FMCW) modulator based on the phase-locked loop (PLL) with nested sub-PLL structure in a 65-nm CMOS process. With the sub-PLL, the low-pass effect in phase domain is realized, reducing the noise folding effect, quantization noise, and spurs due to the delta sigma modulator (DSM). To achieve good stability and phase noise performance, both the phase-domain model and the phase noise model are analyzed and simulated. Based on these models, the chirp linearity is discussed and simulated, which helps to determine the design parameters and verifies the linearity improvement. The measurement results illustrate that in fractional-N mode, the nested-PLL achieves the phase noise of -91 dBc/Hz at 1-MHz offset frequency and the fractional spurs of less than -54 dBc at 30.78-GHz output frequency. In FMCW mode, the proposed modulator achieves a triangular chirp with 1.08-2.16-GHz bandwidth at about 32-GHz center frequency. In addition, the measured root mean square (rms) frequency errors of 400 and 770 kHz are achieved with the ramp slopes of 1.08 GHz/93 μs and 2.16 GHz/93 μs, respectively. Measurement results prove the improvements of the phase noise and chirp linearity with the sub-PLL. Including all pads, the chip occupies a silicon area of 1.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and consumes 62-mW dc power.