A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator

Abstract

This paper presents a low-power low-jitter PAM4 clock and data recovery circuit. A novel quarter-rate linear phase detector (QLPD) is proposed to lower the recovered clock jitter. A self-biased PLL based multiphase clock generator (MCG) is proposed to reduce power consumption. Fabricated in 40-nm CMOS process, the prototype achieves error-free operation at 32-Gb/s input data rate with 0.46-pJ/bit bit efficiency and 352.6-fs integrated jitter of the 4-GHz recovered clock. The measured jitter tolerance at BER of $ is higher than 0.35 UI PP with the corner frequency at about 10 MHz.