A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique

Abstract

In this paper, a high speed low power consumption Flash-SAR ADC with shared preamplifier and distributed comparators has been presented. Also, a brand-new 3-D MOM unit capacitor which has a capacitance of 1fF is used as the basic capacitor cell of this capacitor array. The 320MS/s 7-b Flash-SAR ADC has been verified in TSMC IP9M 65nm LP CMOS technology. The post-layout simulation result shows that this design achieves an effective number of bits(ENOB) of 6.115bit, a signal-to-noise plus distortion ratio (SNDR) of 38.58dB and a spurious-free dynamic range (SFDR) of 51.87 dB at the sampling frequency of 320MS/s. The Flash-SAR ADC (140um 160um) core with an area of 0.0224mm2 and consumes 0.92mW under the voltage of 1.2V. The figure of merit (FOM) of the Flash-SAR ADC achieves 39fJ/conv.