A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist

Abstract

The implementation of the six-transistor (6T) static random access memory cell in deep submicrometer region has become difficult due to the compromise between area, power, and performance, with local and global variations only exacerbating the problem further. To impede the read–write conflict of the 6T cell, the seven-transistor (7T) cell with a noise-margin-free read operation has previously been proposed. But it severely lags in terms of its write ability at lower voltages due to its single-ended write operation. Its single-ended read operation also degrades severely in performance when operating in subthreshold (ST) region. To combat these problems, we propose a 7T cell which operates in the ST region down to 0.4 V with improved dynamic write ability. The novel topology also helps reduce power consumption by achieving a lower data retention voltage point. A read assist has been proposed to greatly enhance the performance of the single-ended read operation in ST region. Large improvements in various performance metrics of the proposed cell have been attained while simultaneously achieving a low area of $0.254~\mu \text{m}^{2}$ per bit cell on the 32-nm technology node.