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Abstract
This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within a predriver stage for multitap multilevel signal summation in charge domain at the transmitter front end. Such a unique approach isolates the signal summing node from the output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling and level-shifting at the predriver output without sacrificing its speed. A level-mismatch-correction scheme is adopted to effectively enhance PAM-4 signaling quality. Implemented in a 28-nm CMOS, the designed transmitter prototype achieves a peak data rate of 32 Gb/s and an energy efficiency of 2.1 mW/Gb/s.
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