Abstract
SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
