A 30MHz Delay-Line-Based Buck Converter with 5.7%-94.8% Switching Duty Cycle

Abstract

As the switching frequency of DC-DC converters continues to increase, the influence of circuit delays is also increasing, which poses a great challenge to the design of a comparator. A 30MHz delay-line-based buck converter is proposed in this paper, which eliminates the need for a traditional PWM comparator, simplifies the complexity of the circuit and logic and solves a series of problems caused by comparator delays at high switching frequency. A delay-line-based voltage-to-duty-cycle (V2D) controller is used to replace the traditional ramp-comparator-based V2D controller to achieve a wider duty cycle range. The proposed DC-DC converter has been designed and simulated by Cadence software based on the 0.18-µm mixed signal CMOS process. The tunable duty cycle ranges from 5.7% to 94.8%, allowing the converter to regulate the output from 0.1V to 1.7V with 1.8V input. With a step of 400mA in the load current, the setting time is around 2µs. The maximum load current is 1A and the peak efficiency is as high as 94.5% with 1.5V output.