A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier

Abstract

RF power amplifiers (PA) implemented in a scaled CMOS technology typically have a low maximum output power because they operate from a low supply voltage. This paper proposes an array RF PA able to deliver a large output power from a large supply voltage through the use of three techniques illustrated in Fig. 5.4.1: (1) series-parallel transformers, (2) transistor stacking, and (3) amplifier stacking. First, the array RF PA employs series-parallel combinations of transformers to provide simultaneous impedance transformation and power combining over a wide bandwidth. The integrated on-chip impedance transformation is more robust and reproducible than off-chip matching using discrete passive components. Second, stacking transistors in the array RF PA increases the output power provided by each of the unit PA stages comprising the array. Third, two PAs are stacked [1]. The two stacking methods increase the operating supply voltage, thus making possible an RF PA operating directly from a battery without the need for a DC-DC switching regulator to generate a low PA supply voltage. A prototype 2×4 array RF PA with a -3dB bandwidth of 1.9GHz has been integrated in a standard 65nm CMOS technology. The array RF PA can deliver 30.3dBm (28.2dBm) of output power at 5.3GHz when operating from a 6.35V (4.8V) supply with 17.8% (20.6%) power-added efficiency (PAE).