Abstract

MOS-only memristor emulators that work solely on the intrinsic capacitors of the transistors can have a high frequency operation feature and a low occupied chip area. This paper presents a memristor emulator consisting of two MOSFETs (i.e., M0 and M1) without any external elements and power supplies except for grounded M1’s source and body. When M0 and M1 are p-channel/n-channel MOSFETs, the proposed memristor emulator is named PMME/NMME. The post-simulation i−v curves of PMME/NMME exhibit pinched hysteresis loop shapes before the frequency of their sine inputs increases to 300 MHz. The occupied layout area of PMME/NMME is 1.8 * 2.57 μm2 in the Cadence design environment with 65 nm CMOS process. Furthermore, four stateful logic circuits based on PMMEs and NMMEs are presented. The feasibility of the proposed memristor emulator is verified with discrete p-channel MOSFETs of CD4007.

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