A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera

Abstract

This article presents an 8.3-Mpixel 60-frames/s CMOS image sensor with skew-relaxation analog-to-digital converters (ADCs) and an on- chip testable ramp generator for low-noise and high-sensitive surveillance cameras. Three novel techniques are proposed to improve the circuit noise and linearity characteristics under low illuminance. A local multiply circuit (LMC) reduces a differential non-linearity (DNL) of the column-wise ADC by halving the delay difference of long-distance wiring signals. A noise suppression ramp generator (NSRAMP) can reduce the horizontal streak noise to 1/4 by compressing only the noise component in the low-light signal. A flexible test circuit (FTC) enables high-speed on- chip test of the ramp generator separately from the ADC characteristics. Test chip fabricated in 55-nm backside illumination (BSI) process achieves DNL of +0.42 LSB/−0.32 LSB and the horizontal streak noise of 30.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> Vrms. DNL is reduced by 27% (circuit skew) and 50% (propagation skew), respectively, and the horizontal streak noise is also reduced by 72% compared to the conventional scheme.