A 3 mW 1.2–3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth

Abstract

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of [Formula: see text]-stage ring-VCO with a resolution of [Formula: see text] in a time period of [Formula: see text]. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40[Formula: see text]nm CMOS process and operates from 1.2[Formula: see text]GHz to 3.6[Formula: see text]GHz with 8-phase outputs. The total lock time is less than 3[Formula: see text][Formula: see text]s including calibration and PLL closed-loop locking processes. Operating at 3.2[Formula: see text]GHz, the in-band phase noise is better than [Formula: see text][Formula: see text]dBc/Hz and root-mean square (RMS) jitter integrated from 10[Formula: see text]KHz to 100[Formula: see text]MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5[Formula: see text]ps and [Formula: see text][Formula: see text]dBc/Hz, respectively. The clock generator consumes only 3[Formula: see text]mW from 1.1[Formula: see text]V supply at high-frequency end and 1.6[Formula: see text]mW at low-frequency end. The active area is only 0.04[Formula: see text]mm2 including on-chip loop filter and auto-calibration circuits.