A 3.2-GHz Quadrature Error Corrector for DRAM Transmitters, Using Replica Serializers and Pulse-Shrinking Delay Lines

Abstract

For DRAM transmitters, in this letter, we propose a quadrature error corrector (QEC), in which clock signal phase errors are corrected using two replicas of the 4:1 serializer of the output stage. Pulse shrinking is used to compare and equalize the outputs of these two replica serializers. To validate the effectiveness of the QEC, a prototype quarter-rate transmitter including our QEC was fabricated in 65-nm CMOS. Adopting our QEC, the experimental results show that the output phase errors of the transmitter are reduced to a residual error of 0.8 ps and the output eye width and height are improved by 84% and 61%, respectively, at a data rate of 12.8 Gb/s.