A 3.125Gbit/s Parallel Optical Receiver in 0.13-{mu} CMOS with Direct Crosstalk Power Penalty Measurement Capability

Abstract

We introduce a new method to measure the crosstalk power penalty in an arrayed environment by using an on-chip pseudorandom-bit-sequence generator to drive the aggressors. The proposed method is implemented in a three-channel 3.125-Gbit/s/ ch parallel receiver. Experimental results are presented including measurements of bit-error rate and crosstalk power penalty for 2.5and 3.125-Gbit/s operations. The measured crosstalk power penalty is less than 1 dB at both data rates. The test chip was designed in a standard 0.13-mum CMOS process