A 2x2 bit Vedic multiplier with different adders in 90nm CMOS technology

Abstract

Adders play an important role in various arithmetic circuits such as multipliers. Speed and power consumption become very vital in multiplier design consideration to conserve energy. In this paper, a 2x2 bit Vedic multiplier has been designed using 3 different adder circuits. The first circuit is utilizing two half adders which used 3 transistors exclusive OR gate (3T XOR), the second circuit used two full adders with 6 transistors XOR (6T XOR) gate and the last circuit used two 13 transistors hybrid full adders (13T HFA). The adders used are combined with four AND gates to form a multiplier module to execute a Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. The 2x2 bit multiplier is simulated using Synopsys Custom Tools using General Process Design Kit (GPDK) of 90 nm...