A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup

Abstract

A high-performance clock generator with extremely low jitter, area, and power consumption is the key building block in the emerging Internet of Things (IoT) to connect billions of devices. Recently, digital phase-locked loops (DPLL) [1,2] have been developed to eliminate the bulky loop filter (LF) in type-II charge-pump PLLs. However, they suffer from quantization noise and spurs, requiring complex calibration techniques. Therefore, type-I reference-sampling PLLs are gaining popularity [3, 4] to achieve wider bandwidths in smaller areas. A passive sampling phase detector (SPD) has a much lower noise contribution than a charge pump. But, a fractional-N implementation requires a digital-to-time converter (DTC) to align the input clocks of the SPD for spur mitigation [3]. Precise gain and nonlinearity calibrations are needed as the DTC delay can vary significantly with process-voltage-temperature (PVT) variations. This increases the complexity and loop convergence time, which are not preferable for IoT applications. A capacitive digital-to-analog-converter (CDAC)-based approach proposed in [4] relies on an accurate voltage reference provided externally, which also requires a calibration across PVT in practical implementations. This work presents a voltage-interpolation (VI) technique based on the capacitor charge sharing in a type-I sampling PLL to achieve the fractional-N operation and, therefore, eliminate a DTC or voltage reference and the associated complex calibration logic, providing fast phase locking. Furthermore, noise is minimized using a passive switch-capacitor-based VI (SC-VI), and the fractional frequency-synthesis resolution is enhanced utilizing a AZ-VI. Moreover, for edge-compute platforms, fast shutdown and restart of the clocking subsystem are necessary for efficient power management by transitioning among different power states. To enable such a requirement, the PLL is reconfigured to inject energy into the crystal for quick startup. Prior energy injection techniques in crystal oscillators for fast startup [5] used a dedicated ring voltage-controlled oscillator (VCO), which exhibited startup time uncertainty due to high jitter and frequency drift across PVT, requiring an additional frequency calibration step. In contrast, reusing the LC VCO inside a PLL that follows the crystal oscillator to perform frequency synthesis introduces less noise and frequency drift for robust startup while eliminating the VCO frequency calibration step. In addition, the chirp mechanism, which is similar to [5], sets the VCO frequency very close to the desired steady-state value, providing faster PLL locking.