A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression

Abstract

Ring voltage-controlled oscillator (VCO) based PLLs have several advantages over LC-VCO based PLLs, like smaller chip area, wider frequency tuning range and multi-phase output signals. However, the inferior jitter/phase noise of ring VCOs has always been the bottleneck of the overall PLL jitter/phase noise performance. To suppress ring VCO's phase noise, feedforward phase noise cancellation (FFPNC) techniques [1]–[4] and feedback phase noise cancellation (FBPNC) technique [5] are widely researched. However, most FFPNC and FBPNC based structures require numerous additional blocks, like complicated phase noise extraction circuits, long voltage-controlled delay line, or additional clock generation circuits, which consumes significant extra area and power. In order to suppress the phase noise of the ring VCO with minimal area and power consumption, this paper proposes a dual-path sub-sampling PLL (SSPLL) architecture incorporating an FBPNC technique. The SSPLL's bandwidth is extended with a compensated phase margin due to the proposed FBPNC technique, as a result, the in-band phase noise contributed by the ring VCO is effectively reduced.