A 28 nm 81 Kb 59–95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output

Abstract

Computing-in-memory (CIM) based on Resistive RAM (ReRAM) can effectively improve the energy efficiency and throughput of artificial intelligence (AI) edge devices. However, due to the complex hardware structure and the non-ideal factors of the circuit, improving the processing precision will sharply reduce the energy efficiency and reliability of AI computing. In this work, a high-performance ReRAM-based CIM accelerator is presented to solve the above problems using: 1) a 4T2R cell to replace the traditional 2T2R cell for weight storage with higher on/off ratio and smaller computing current; 2) a pulse width modulation converter to realize linear input with lower performance cost; 3) a voltage-to-time-to-digital based converter to reduce the power consumption and area of the output circuit. An 81Kb ReRAM based accelerator was designed using 28nm process with 1-4b input/weight/output. To verify the reliability of the accelerator, non-ideal factors are added in training and testing. For evaluation, a network is built for CIFAR-10 based on the proposed accelerator. The proposed accelerator achieves a high processing frequency of 167-500 MHz and an energy efficiency of 95.3-59 TOPS/W for 1-4b precision operation with an FoM (input-precision × weight-precision × energy efficiency) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.6\times $ </tex-math></inline-formula> higher than prior work.