Abstract
This paper describes a silicon receiver for a multiple-input multiple-output (MIMO) wireless channel that supports up to 28.8 Mb/s using a 4 /spl times/ 4 QPSK configuration over a 5-MHz frequency selective channel. The architecture has two key components: a space-time equalizer that mitigates both spatial and temporal effects of the channel, and a maximum likelihood detector with approximate a posterior probability (ML-APP) soft estimates of the transmit vectors over the MIMO configuration. The space-time equalizer uses an adaptive tap training process that includes a pilot correlator to reduce adaptation noise. The device is 685 k effective logic gates (11.6 mm/sup 2/) in 0.18-/spl mu/m 6LM CMOS.
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