A 2.7V 350/spl mu/W 11-b algorithmic analogue-to-digital converter with single-ended multiplexed inputs

Abstract

A low-power low-area CMOS algorithmic A/D converter that does not require trimming nor digital calibration is presented. The topology is based on a classical cyclic A/D conversion using a capacitor ratio-independent computation circuitry. All the nonidealities have been carefully analyzed and reduced by proper choices of design and layout solutions. As a result the errors coming from opamp offset and finite open-loop dc gain, switch charge injection and clock feedthrough, parasitic capacitors, and intrinsic noise sources are reduced under the LSB level. To process a multiplexed (8 channels) single-ended analogue input, an efficient single-ended to fully differential circuit has been presented. The converter achieves 11 bit accuracy in the Nyquist band at a sampling rate of 8kSps. The total power dissipation is only 350/spl mu/W at 2.7V supply voltage. The active area is 0.3 mm/sup 2/ in a 0.35 /spl mu/m 5 metal levels CMOS technology with double-poly linear capacitors.