A 270-mV 6T SRAM Using Row-Based Dual-Phase VDD Control in 28-nm CMOS

Abstract

This paper presents a 28-nm 32kb 6T static random access memory (SRAM) operating down to the sub-threshold regime. This design employs a dual-phase VDD (DPVDD) control technique in a row-based manner to reduce the minimum functional voltage (Vmin) below the threshold voltage of the transistor (Vth). With the proposed DPVDD technique, during the read operation, the ratio of the read current to the leakage current caused by the unselected bit-cells on the same bit-line is increased by a temporally boosted cell VDD, which increases the signal swing on the bit-line and minimizes the stability degradation caused by the leakage current. In addition, the proposed DPVDD can enhance the stability of the half-selected cells to mitigate the half-select disturbance. A 32-kb 6T SRAM test chip was implemented in 28-nm CMOS technology with a macro area of 0.028 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurement results show that the SRAM with the proposed DPVDD achieves Vmin of 0.27 V and the minimum energy of 0.041 fJ/bit.