A 27–41 GHz Frequency Doubler With Conversion Gain of 12 dB and PAE of 16.9%

Abstract

A 27–41 GHz monolithic balanced frequency doubler fabricated using the 0.13 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> SiGe BiCMOS technology is presented in this letter. The balanced doubler consists of a balun, a driver amplifier (DA), a common-base (CB) doubling core and a medium power amplifier. The CB topology is used to increase the bandwidth and for the ease of matching with the balun. The proposed frequency doubler attained a measured gain of 16.8–19.8 dB, an output power of 1.3–4.3 dBm, and a fundamental rejection of better than 25.7 dB (from 27 to 41 GHz) at an input power of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-15.5 ~{\rm dBm}$</tex></formula> . An maximum output power of 8 dBm with dc power consumption of 35 mW and corresponding power added efficiency (PAE) of 16.9% have also been achieved. The chip size is 0.75 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times \,$</tex> </formula> 0.45 mm.