A 26 μW area efficient bio-potential acquisition system with feed-forward DC offset cancellation

Abstract

This paper presents a low-power front-end interface Application Specific Integrated Circuit (ASIC) for bio-potential acquisition. A new feed-forward Direct Current (DC) blocking scheme is proposed for current feedback instrumentation amplifier (CFIA) to reduce the DC electrode offset. The proposed scheme effectively uses an impedance scalar to reduce the size of the capacitor to make it fully on-chip. Apart from electrode offset reduction, chopper stabilization is also utilized for internal offset reduction as well as low-frequency noise removal. Programmable gain and programmable bandwidth units are used to make the interfacing circuit configurable for different type of bio-potentials. A feature extraction channel is included within the interface ASIC to reduce the digital processing overheads for beat detection in Electrocardiogram (ECG) signal processing. The complete circuit is designed and simulated in United Microelectronics Corporation (UMC) 180 nm process technology and the simulation results are presented. Simulation results show that the proposed interface is able to suppress up to 50 mV of DC electrode offset while the total power consumption is 26 μW with a supply of 1.8 V.