A 2.5GHz Low Power Consumption and Low Phase Noise PLL with Lock Detector in 55nm CMOS

Abstract

A low phase noise and low power consumption charge pump phase locked loop (CPPLL) frequency synthesizer based on 55nm CMOS technology is presented in this paper. It is designed to generate the local oscillator frequency ranging from 2.40GHz to 2.48GHz for a Bluetooth Low Energy (BLE) transceiver. A self-biasing linear trans-conductance technique is used in the voltage controlled oscillator (VCO) for the improvement of phase noise. In order to reduce the effect of spur on noise, a third-order sigma-delta modulation (SDM) is utilized. A lock detector based on dichotomy is used for the phase locked loop (PLL) to select the switched capacitor code automatically and lock faster. The proposed PLL could operate from 2.33 GHz to 2.59 GHz. According to the post-simulation results at 4.88GHz, the phase noise at 1 MHz offset of the VCO and the PLL is - 113.17dBc/Hz and -106.6dBc/Hz, respectively. The total power consumption is 2.4 mW and the whole PLL area is only O.27xO.55 mm2.