Abstract
A 256K DRAM with a die size of 45 mm/SUP 2/ has been developed using NMOS technology and TaSi/SUB 2/ on gate electrodes, interconnections, and nonfolded bit lines. The 90-/spl mu/m/SUP 2/ cell uses HiC implants to gain a storage capacitance of 55 fF for improved soft error immunity. Laser activated redundancy is incorporated on the chip, which is made completely testable. Five different postrepair diagnostics are available, allowing efficient testing and easy failure analysis of repairable devices. In the nibble mode operation the data are held valid during the entire CAS precharge time, providing ample time for proper sensing, even at minimum cycle parameters. With this novel feature the high system data bandwidth promised by the very short nibble mode cycle time can be realized more easily than with the standard solution.
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