A 2.56 Gbps Asynchronous Serial Transceiver with Embedded 80 Mbps Secondary Data Transmission Capability in 65nm CMOS

Abstract

A new asynchronous serial transceiver is proposed that is capable of transmitting and receiving a secondary data stream along with the primary data stream on a single asynchronous serial link. The proposed transceiver embeds the secondary data stream by modulating the phase of the primary data in accordance with it. The receiver recovers both the primary and secondary data simultaneously. In a standard receiver, which is not equipped with the phase demodulation capability, the secondary data appears as jitter of the primary data. The jitter caused by the secondary data still falls within the jitter budget of the transceiver, and having this much jitter would not adversely affect the functionality of the primary data recovery. The proposed system can be widely used in many data communication applications such as for transmitting a hidden signature for data authentication, or as control and/or additional data in an existing serial link. A prototype transceiver, implemented in a 65 nm CMOS process, demonstrates the proposed concept with 2.56 Gbps primary data and 80 Mbps secondary data channels.