A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRs

Abstract

This paper describes a 2.5-3.125 Gb/s quad transceiver with second order analog DLL based clock and data recovery (CDR). The proposed CDR can tolerate large frequency offsets with no jitter tolerance degradation. Fabricated in a 0.15 /spl mu/m CMOS process, the 1.9 mm/sup 2/ transceiver front-end operates from a single 1.2 V supply and consumes 65 mW/channel of which 32 mW is due to the CDR. The CDR jitter generation and high-frequency jitter tolerance are 5.9 psec-rms and 0.5 UI, respectively, when a 3.125 Gb/s 2/sup 23/-1 PRBS data with 800 ppm frequency offset is applied.