A 250-MHz skewed-clock pipelined data buffer

Abstract

A synchronous dual-port memory employing a three-transistor (3T) dynamic cell has been designed for use as a high throughput embedded data buffer in digital switching and signal processing applications. Skewed-clock pipelining is used to achieve operation at frequencies as high as 250 MHz with a low register element count. The 3T cell provides separate read and write access ports while occupying less than half the area of a conventional dual-port SRAM cell. On-chip Hamming error correction coding (ECC) is used to enhance the fault tolerance of the memory, A 25-kb experimental prototype has been integrated in a 0.8-/spl mu/m CMOS technology; it occupies a die area of 3800 /spl mu/m/spl times/1600 /spl mu/m and dissipates 420 mW while operating at 250 MHz.