A 250 MHz 11 bit 22 mW CMOS low-hold-pedestal fully differential sample-and-hold circuit

Abstract

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes improved bootstrapped input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 250 MHz of sampling frequency with less than ?70 dB of total harmonic distortion corresponding to 11 bits for an input 60.8 MHz sinusoidal amplitude of 1.8 V pp at a 3 V supply. The total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.8 V step input, and 1.8 V pp full-scale differential input range are achieved. The circuit dissipates 22 mW with a 3 V power supply.