Abstract
This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.
Highlights
While scaled CMOS technology continues to enhance on-chip operating speeds, the power dissipation increases at the same time
Their output swings were around 350 mV, but their performance was degraded. This is due to the lane-to-lane interference of signals and power lines, which introduced higher deterministic jitter (DJ) that deteriorated the signal integrity of the output signals.2019, The8,total at9
The receiver, a pre-stage voltage shifter was introduced to implement commonInmode voltage a pre-stage common mode voltage shifter was introduced to implement the common mode conversion, and a rail-to-rail comparator embedded with a shaping buffer was utilized to voltage recover conversion, and a rail-to-rail with of a shaping buffer wasdriver utilized to recover thea the input signal
Summary
While scaled CMOS technology continues to enhance on-chip operating speeds, the power dissipation increases at the same time. The architecture of LVDS drivers is divided into fully-differential NMOS-only style style [12], style MOS [13] and complementary [14,15,16]. NMOS-only style LVDS driver, shown, works well if the supply voltage (VDD) is 2.5 V is. To overcome the signals supply isvoltage headroom issues, PMOS-only (shown swing of the output signals is required, which would cause the transistors (M1a and M2a) to cut off. The inherent speed complementary MOS (shown in Figure 2c) LVDS drivers need to be addressed. Comparing the above-mentioned same speed as CMOS style drivers, the size of the transistors must be increased. 2 describes the architecture of the LVDS proposed operate at a data rate up to 2.5 Gbps, and is fully compatible with ANSI/TIA/EIA-644-A standards.
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