A 24GHz Radar Receiver in CMOS

Abstract

This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or moving objects. The feasibility of realizing these concepts in hardware with a small form factor could accelerate commercialization and initiate new product opportunities. Minimizing the receiver power consumption to the 15mW range enables 4 hours of continuous operation from a 1.2 gram button sized lithium battery. CMOS technology has the potential for realization of both the RF transceiver and baseband processor in a single chip. An understanding of the functional requirements is a prerequisite for system optimization. The 15mW power budget necessitates the continuous nature of FMCW radar configuration, which obviates the requirement for a power-hungry transmitting amplifier. FMCW radar in short-range applications benefits from the phase noise correlation between transmitted and received waveforms, which may be exploited to lower the power consumption of the LO generation circuits. A choice for the heterodyne receiver architecture mitigates erroneous detection due to second-order intermodulation distortions caused by interfering radar transmitters nearby, accuracy degradation due to frequency pulling of the ultra-wideband VCO, and signal quality degradation due to flicker noise generated by CMOS transistors. The power dissipation and hardware overhead of a heterodyne receiver are relaxed by proper frequency planning and elimination of the image-reject filter due to frequency chirping property of the FMCW signal. A frequency downconverter for the radar receiver is realized by integrating a LNA, a Gilbert-type mixer, and a VCO running at the carrier frequency. A varactorless frequency tuning scheme is proposed for the VCO which breaks through the conventional trade-offs seen in continuous and wideband mm-wave frequency generation between capacitance tuning ratio, quality factor, and operating frequency in CMOS design. Inductive frequency tuning is enabled by a transformer resonant tank which exploits the gyration (90 degree) across the input/output terminal voltages of a transconductor. The parallel resonant frequency is controlled by sweeping the sign and magnitude of the transconductance. The VCO is frequency-agile, and is continuously tunable by altering the DC bias current of the transconductance cell. Adaptability between frequency tuning and power consumption is possible. Two VCO test circuits are reported in this thesis. (1) A proof of concept in 0.13um RF-CMOS consumes 43mW from a 1.2V supply. The frequency coverage is from 23.2GHz to 29.4GHz (23.6% tunable range) and the phase noise is -92.6dBc/Hz at 1MHz frequency offset. (2) A miniaturized prototype is implemented in 90nm CMOS for the radar receiver. It consumes 5.7mW from a 1.0V supply. Its maximum frequency range is from 18.6GHz to 21.2GHz (13.1% tunable range) and phase noise is at 1MHz frequency offset. Operation of a CMOS LNA in the moderate inversion region and at a frequency approaching the transistor's operational limit deteriorates its power gain and noise figure. A two-step LNA optimization algorithm is proposed in this thesis which addresses both the device and circuit levels. Transistor dimensions and biasing are set for optimal power gain, noise figure, linearity, bandwidth, and matching network loss. Partitioning the limited power budget across multiple gain stages maximizes the overall power gain. Optimizing the transistor's interaction with bilateral power flows in a multi-stage amplifier is facilitated by Smith chart based visualization and a computer-aided design methodology. The advantages of this methodology are demonstrated by design examples. Current-feedback by a 3-port transformer in a cascode LNA is proposed in this thesis in order to increase the power gain and lower the noise figure performance under low-power conditions. The feedback modifies the relationship between the input referred voltage and current noise sources of a common-gate MOS transistor, and thereby fulfills the internal interface impedance conditions in the cascode LNA for optimal power gain and noise figure matching. A two-stage, single-ended, current-feedback cascode LNA prototype is realized in 90nm CMOS. Physical implementation with multiple magnetic components, signal integrity associated with current return path, and circuit simulations employing an S-parameter model are addressed and emphasized in the LNA development. Consuming just 3mW from a 1V supply, the LNA achieves 14.5dB peak power gain, a -3dB gain bandwidth of 5.0GHz. The noise figure varies from 4.9dB to 5.6dB across a 22GHz and 26GHz RF bandwidth, and the IIP3 is -6.0dBm. The frequency downconverter is realized by integrating the inductive-tuned VCO and current-feedback LNA with a differential Gilbert-type mixer. Isolation of the LNA single-ended current return path from the rest of the receiver is maintained by a 8-port transformer balun preceding the mixer. This receiver RF front-end draws 10.7mW from a 1.0V supply, and delivers 12.6dB peak power gain, -3dB bandwidth of 1.25GHz. The noise figure varies from 10.6dB to 11.5dB across the RF bandwidth, and the IIP3 of the downconverter is -12.1dBm.