Abstract
In this paper, the optimized design strategies for the implementation of a CMOS digitally controlled oscillator (DCO) are investigated. Moreover, the boosting mechanism for a DCO with and without negative resistance is considered. The proposed design methodology is based on an in-depth mathematical analysis of the startup condition and amplitude of oscillation. This approach results in an optimized topology for a Colpitts Clapp-DCO (CC-DCO). The improved performance is achieved through the negative resistance boosting mechanism. The negative resistance enhances the startup time and increases amplitude stabilization across a wide tuning range (TR). Moreover, it improves the phase noise (PN) performance while suppresses the amplitude-to-phase conversion. The proposed 24-GHz CMOS enhanced CC-DCO (ECC-DCO) is implemented in 65-nm TSMC CMOS process. It can effectively reduce the startup time by 41%. Also, it boosts and stabilizes the amplitude across a TR of 29%. The amplitude varies by 1.5% across the 22-29-GHz TR. The ECC-DCO consumes 12.8 mW. It shows a PN of -106 dBc/Hz at 1-MHz offset frequency and achieves -185-dBc/Hz figure of merit (FoM) and -194-dBc/Hz FoM for tuning.
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