A 24 GS/s single-core flash ADC with 3 bit resolution in 28 nm low-power digital CMOS

Abstract

This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit (FOM) of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.