Abstract
This paper presents a high-speed single channel pipeline analog-to-digital converter sampling at 2.4 GS/s which, to the authors' best knowledge, is the fastest reported for pipeline converters. The use of a time-borrowing clocking scheme eliminates the comparator latency from the critical path and together with the use of fast open-loop current-mode amplifiers the high sample rate is achieved. Implemented in a 65nm general purpose CMOS technology the effective number of bits is above 4.7 in the Nyquist band, being 5.4 and 4.9 at DC and Nyquist respectively. This shows that very fast pipeline ADCs are possible to implement as key building blocks in interleaved structures.
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