A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope

Abstract

A 24 GHz self-calibrated all-digital frequency-modulated continuous-wave (FMCW) synthesizer is presented in this article. A multi-bank digitally controlled oscillator (DCO) is employed to provide adequate frequency tuning range and high frequency resolution. A full background self-calibration scheme is proposed to linearize the DCO tuning curve for highly linear and fast chirp generation. An overlap compensator based on an adaptive lookup table (LUT) is utilized to eliminate the frequency overlaps between adjacent DCO tuning bands. The compensation words in the LUT are altered by least-mean-square (LMS) algorithm for robust and precise matching. A ramp tracker, which features real-time ramp tracking with zero steady-state phase error, is employed to estimate and stabilize the frequency ramp. Implemented in 40 nm bulk CMOS, the FMCW synthesizer prototype consumes 28 mW with a 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. The maximum chirp bandwidth is 3.2 GHz, corresponding to 13.33% of the center frequency. Measurement results show that the root-mean-square (RMS) frequency error is reduced by 1/10 with self-calibration after 2 ms convergence time. The maximum chirp slope is up to 320 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> with 309 kHz RMS frequency error. The minimum RMS frequency error is 7.35 kHz under 5 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> chirp slope, corresponding to 0.0002% of the chirp bandwidth.