Abstract

ABSTRACTThis paper describes a 24 GHz frequency synthesizer for automotive collision avoidance radar. This circuit is designed using 65 nm CMOS technology. The voltage-controlled oscillator (VCO) in modified current-reuse configuration where transistors are biased in subthreshold region to save power consumption. The output frequency is 24 GHz, and the reference frequency is 100 MHz. The proposed circuit showed low power consumption of 3.52 mW with the supply voltage of 0.9 V. The VCO tuning range was 7.5% at 24–25.8 GHz, and the VCO also showed a low phase noise of −108.8 dBc @1 MHz and −131.50 dBc @10 MHz. The phase-locked loop showed fast settling time of 3.1 ns with the divider ratio of 240. The proposed circuit showed a low phase noise of −104.32 dBc @1 MHz and −127.02 dBc @10 MHz. Peak-to-peak jitter was 3.5 ps, and rms jitter was 0.754 ps.

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