A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL

Abstract

This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of ΔΣ modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 μm CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .