Abstract
This paper presents a continuous-time (CT) quadrature bandpass (QBP) ΔΣ ADC which is reconfigurable in terms of quantizer resolution, bandwidth (BW) and IF. It is designed for use in a low power low-IF multi-band transceiver system. In simulations the presented implementation in a 130nm RF CMOS process achieves a resolution of 10.5 bit. Additionally, a total power consumption of 2.3mW from an 1.2V supply voltage is simulated. The BW of the 3rd order QBP filter can be set to 0.5, 1.0 or 2.0MHz together with the IF. Likewise the loop quantizer is capable of single and dual-bit analog to digital conversion. Separate digital to analog converters (DAC) for both modes are used in the feedback of the ΔΣ loop. Furthermore an improved data weighted averaging (DWA) algorithm is presented to control the dual-bit DAC unity cells and cope with the DACs I/Q mismatch.
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