A 22 mW 512 MHz CMOS continuous time sigma delta ADC in 1.2 V with 16 MHz signal bandwidth and 70 dB dynamic range

Abstract

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130 nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60 dB SNR and a 59.3 dB signal-to-noise-plus-distortion ratio over a 16 MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2 V supply.