Abstract
This paper presents a single-chip 240 GHz frequency multiplier chain in a 130 nm SiGe BiCMOS process. It consists of two balanced output doublers and an integrated high-gain high output amplifier. To enhance the output power, the output of the 212–260 GHz doubler adopts a current power combing architecture. The optimized second harmonic reflectors are introduced in the 212–260 GHz doubler to further increase output power without sacrificing the bandwidth. The first-stage wideband 120 GHz doubler cascaded with a driving amplifier is employed to drive the last-stage doubler with sufficient power. The measured peak output power is 5.5 dBm at 252 GHz, and the 3-dB bandwidth is from 212 GHz to 260 GHz. The proposed frequency multiplier chain consumes 270 mW DC power from a 3.3 V power supply. The peak DC-to-RF efficiency of the frequency multiplier chain is 1.4% corresponding to an 8% collector efficiency.
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