A 210fs RMS jitter 187.5 MHz-3GHz fractional-N frequency synthesizer with quantization noise suppression techniques and chopping differential charge pump for SDR applications

Abstract

This paper proposes a low noise fractional-N frequency synthesizer with quantization noise suppression techniques and a chopping differential charge pump. A level-shift-less phase frequency detector and a chopping differential charge pump are proposed to improve matching performance and suppress in-band phase noise of the frequency synthesizer. The combination of a 4/4.5 divider and a notch filter enable the design of an efficient system to suppress quantization noise and improve in-band and out-band phase noise by 3 dB and 6 dB, respectively. With all these techniques, the frequency synthesizer is implemented in a standard 65 nm CMOS process, achieving 210fs root mean square jitter and less than −70dBc reference spur with operating range from 187.5 MHz to 3 GHz.