Abstract
A 20-GHz low-power low-noise amplifier (LNA) in 65-nm CMOS is presented. The LNA is cascaded with a single-ended gm-boosted common-gate (CG) stage and a differential neutralized common-source (CS) stage. The current-reuse technique is employed to save the power consumption. The LNA achieves a measured power gain of 14.9 dB at 21 GHz with a -3-dB bandwidth of 4.8 GHz. The lowest noise figure (NF) is 3.3 dB at 19.5 GHz. The LNA consumes 1.9 mW from a 1-V supply, with a chip area of 600 $\mu \mathbf{m}\times 700 \mu \mathbf{m}$ .
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